1. Field
Exemplary embodiments of the present invention relate to a data sensing circuit and a memory device including the same.
2. Description of the Related Art
Memory devices and diverse integrated circuits use a data sensing circuit for sensing data. Here, the data sensing circuit is a circuit that senses a small voltage difference between logic high and logic low levels of data.
FIG. 1 is a circuit diagram illustrating a data sensing circuit, such as a bit line sense amplifier, used in a conventional memory device.
When a data is read out of a memory cell 101, the voltage level of a bit line BL is changed based on the read data. Since the change in the voltage level of the bit line BL may be too small to be detected, the voltage level of the bit line BL is amplified in a bit line sense amplifier 110. A precharger 120 shown in the drawing is a structure for precharging bit lines BL and /BL to the level of a precharge voltage VBLP before a data is loaded on the bit lines BL and /BL.
The bit line sense amplifier 110 may include a latch circuit for amplifying the voltage difference between the pair of the bit lines BL and /BL. The latch circuit includes two inverters 111 and 112. A pull-up voltage (which is generally a power supply voltage VDD or a core voltage VCORE) is supplied to a pull-up voltage supply terminal RTO and a pull-down voltage (which is generally a ground voltage VSS) is supplied to a pull-down voltage supply terminal SB during a data sensing operation of the bit line sense amplifier 110. The pair of the inverters 111 and 112 receive the pull-up and pull-down voltages and amplify the voltage difference between the pair of the bit lines BL and /BL.
For example, when the voltage level of the bit line BL is a little higher than the voltage level of the bit line bar /BL, the bit line sense amplifier 110 amplifies the voltage level of the bit line BL to a pull-up voltage level, while amplifying the voltage level of the bit line bar /BL to a pull-down voltage level. Conversely, when the voltage level of the bit line bar /BL is a little higher than the voltage level of the bit line BL, the bit line sense amplifier 110 amplifies the voltage level of the bit line bar /BL to a pull-up voltage level, while amplifying the voltage level of the bit line BL to a pull-down voltage level.
In order to accurately sense a data loaded on the pair of the bit lines BL and /BL, PMOS transistors and NMOS transistors that constitute the bit line sense amplifier 110 are to be fabricated under the same processing conditions. However, it is difficult to maintain the processing conditions the same and the transistors may be fabricated to have different characteristics from each other.
Therefore, the transistors of conventional bit line sense amplifiers may have offset features and in order to address the offset features, a method of increasing the capacitance of a memory cell or a method of increasing the voltage level of the driving voltage of the bit line sense amplifier has been introduced. However, the method of increasing the capacitance of a memory cell increases the area of a circuit, and the method of increasing the voltage level of the driving voltage of the bit line sense amplifier increases current consumption.